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ISL5216
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
28:18
FUNCTION
Destination
Destination Field Bit Mapping
DESCRIPTION
28 27 26
25
24
23
22
21
20
19
18
AGCLFGN AGCLF
Path1
Path0
OS
FB
F4
F3
F2
F1
F0
AGCLFGN AGC loop gain select. Only applies to Path 1.
Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).
AGCLF
Path(1:0)
AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude
of this sample (Path(1:0) = 01).
Back End Data Routing Path Selection. (see Back End Data Routing figure)
00
01
10
11
Route output back to filter compute engine input to another FIR in the filter chain.
Route output thru the FIFO and AGC to outputs I1 and Q1.
Route output to I2 and Q2, bypassing the FIFO and AGC. This path
also routes to next channel FIR input.
Route output thru the FIFO and AGC to outputs I2 and Q2.
OS
FB
F(4:0)
Enable output strobe. Setting this bit generates a data ready signal when the data reaches
the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set,
there will be no output to the outside world from this channel, for that output calculation, but
the data will be loaded into its output holding register (OS would not be set when routing the
data to another back end when cascading channels).
Feedback data path. When set, the magnitude and dphi/dt from the cartesian-to-polar coor-
dinate converter block are routed to the filter compute engine input (magnitude goes to the
I input and dphi/dt goes to the Q input). Provided for discriminator filtering.
Filter select. For data recirculated to the input of the FIR processor by path 0 or from the
cartesian to polar coordinate converter output, these bits tell which filter sequencer step
gets it as an input.
31:29
Round Select
31:29
000
001
010
011
100
101
110
111
Round Select (Add rounding bit at specified location).
2 -24 , use this code when downshifting is not used.
2 -23
2 -22
2 -21
2 -20
2 -19
2 -18
no rounding.
Provided for use with the coefficient down-shift bits.
41:32
Data Memory
Block Start
Memory block base address, 0-1023, 0-383 are valid for the ISL5216.
44:42
Data Memory
Block Size
44:42
0
1
2
3
4
5
6
7
Block Size.
8
16
32
64
128
256
512
1024
(modulo addressing is used).
52:45
62:53
Data Memory
Block-to-Block Step
Coefficient Memory
Block Start
20
0-255, usually equal to the decimation factor for the FIR in this instruction.
Memory base address of coefficients, 0-1023, 0-511 are valid on the ISL5216.
FN6013.3
July 13, 2007
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